E-core CPU Backend Engineer for Full-Chip Timing
Become a key member of a team participating in the Integration and Verification of a future Intel CPU. This position requires and Engineer with broad Physical Design and STA skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team.
We are looking for a highly motivated and technically savvy experienced engineer to drive the timing convergence for Full-Chip models. As a FC Design Engineer, you will perform constraints management and STA verification. You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. You will drive timing closure and provide collateral for SOC drops.
What we offer:
We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.
As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.
We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).
We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work!
We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must have a Bachelor's in Electrical/Computer Engineering and 5+ years of experience.
Master's degree in Electrical/Computer Engineering and 4+ years of experience in the industry.
8+ years experience in/with:
Back-end design and/or integration.
Static Timing Analysis including constraint generation, clock stamping and timing closure.
Perl and/or Tcl scripting.
Teamwork and collaboration skills in a high-paced atmosphere.
Productive under demanding schedules.
Excellent communications skills.
Self-motivator with strong problem solving skills.