DFx Verification Engineer
The world is transforming – and so is Intel! Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth.
The Advanced Architecture Development Group (AADG) is a CPU Core development team in Portland, Oregon. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible.
If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we invite you join us to do something wonderful!
Role responsibilities include although not limited to:
Oversees definition, design, verification, and documentation for SoC (System on a Chip) development
Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation
Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs
Contributes to the development of multidimensional designs involving the layout of complex integrated circuits
Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results
Bachelor's degree in Electrical Engineering , Computer Engineering or Computer Science and 3+ years' experience working in Design Verification OR Master's degree in Electrical Engineering, Computer Engineering or Computer Science and 2+ years' experience working in Design Verification.
Experience in developing content in System Verilog, C, C++ or Python
Experience with test development in UVM or OVM framework
Must have Object Oriented based programming skills
Additional qualifications include:
Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems
Intel Architecture ISA and system architecture, x86 assembly language is a plus
Experience in verification or development of serial bus protocols
Experience in debugging features accessed via IEEE 1149.1, 1500 or 1687 TAP networks is a plus
Experience in the use of debug tools: waveforms, trace files and test logs
Exposure to test and testability concepts and must have good debug, troubleshooting and problem solving skills