Software Development and Validation Engineer
We are a Validation IP Center of Excellence organization that validates various IPs that go into a variety of products and segments. These IPs include High Speed IOs (PCIe, USB, TypeC, Fabrics), Low Speed IOs (UART, SPI etc) and FW IPs (Security, Audio, Sensor etc). All our IP are cutting edge technology IPs. Our organization is on a strong growth trajectory across multiple business segments such as Client, Server, IOT and Foundry. We have roles in Software Development, FPGA/Emulation modelling, IP System Validation and Test Chip Development and Validation.
The Software Development Team develops cutting edge validation stimulus to validate the IP Hardware. We have well-defined career opportunities for each individual and we operates in horizontal to provide content and firmware to multiple IPs and SOC product teams.
In this role, responsibilities include, although not limited to:
Planning, Developing and Enhancing Test Content, Test Infrastructure, and Capabilities (using C and/or C++, Assembly, Python, Perl).
Integrate, validate, and debug software across the stack for a specific product, platform, feature, or technology.
Design and develop a software validation environment, the integration, and the enabling of the software stack.
Responsible for the creation of validation plans, automation, associated methodologies, and triage and debugging of failures.
Assesses the state of the art and employs new methods to improve quality, automation, and product release efficiency.
Executing new and existing Tests on the IP FPGA, SOC HFPGA, Emulation models.
Debugging Test Failures/sightings using a variety of Debug Tools to perform characterization of the issue and identify the failing component. This will involve hands on experience in source-level debugging, I2C, oscilloscope and/or bus analyzers.
Interfacing with Architecture, Design, and Pre-Silicon Validation teams in developing, modify and improving tests.
In the FPGA/Emulation team, your role will be of FPGA/Emulation engineer to develop Field Programmable Gate Array (FPGA) and/or emulation models and solutions for next generation IP technology and SoC designs. You will work closely with architecture, design, IP validation and software teams in order to meet project goals.
The responsibilities cover the following:
Develop FPGA/emulation models from Register Transfer Level (RTL) designs using FPGA/Emulation synthesis and place and route tools.
Design and develop interfaces between FPGA/emulation model to software or external hardware using RTL.
Bring up and debug the FPGA/emulation model in simulation and hardware platforms.
Develop tests to validate the functionality of the FPGA/emulation model both in simulation using System Verilog and on hardware platform using Python.
Develop automation flows to integrate and build FPGA/Emulation models in Linux environment using Python/Tcl/Perl.
Communicate with architecture/design/validation/software teams to debug and isolate issues found on the FPGA/emulation models.
In the IP System Validation role, you will define validation strategies, test plans, and methodologies for pre and post silicon functional end to end validation of IPs. You will be responsible for developing and running tests in emulation and post silicon environments to verify that the system meets specification requirements, and finding and implementing corrective measures for failing tests. In this role you will also debug failures in complex systems in both pre- and post-silicon environments. Your key role will be to find HW bugs in the IP. You will work closely with FPGA/Emulation, Software and Design teams. You will also work on many new initiatives to improve validation efficiency and validation coverage.
The Test Chip Development and Validation integrates next generation IP on the latest process nodes enabling post silicon validation of critical systems before they are integrated in System on Chip (SoC) products. In this role you would: Work on Synopsys Fusion Compiler software tool on Automated Place and Route tasks or signoff capabilities such Layout Verification, Extraction, and Static Timing Analysis.
You would be working with a senior group of Design Engineers. Being a small group with quick turnaround times, you would be exposed to large parts of the SoC/ASIC design flow and many of the engineers that take RTL all the way to completed layout for manufacturing (R2G).
In addition to the qualifications listed below, the ideal candidate will demonstrate the following traits:
Team player with keen interest in finding and resolving IP RTL bugs.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience, OR a Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience, OR a PhD degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience in the industry.
Knowledge of modern programming languages (C/C++).
Computer System Architecture/Intel architecture and/or micro-architecture with knowledge of processor, chipset, memory, I/O-subsystems, and bus protocols (one of these- USB, PCIe, Display Port, Type C, PCIe, IOSF, AMBA Bus, Low speed IOs, DDR).
Ability to debug complex platform, HW, SW/FW and environment issues.
VLSI or Auto Place and Route Experience
Exposure to Static Timing Analysis
Silicon/FPGA/emulation modeling and debug experience.
Knowledge of ARM, RISC-V is a plus.
Familiar with DMA architecture.
Familiar with Firmware development.
Familiar with working in Linux development environment is a plus.
Understanding of a subsystem HW/SW stack, including the silicon, all onboard HW components and connectors, external or plug-in adapters and devices, drivers, and applications.
Debugging Test Failures/sightings using a variety of Debug Tools to perform characterization of the issue and identify the failing component. This will involve hands on experience in source-level debugging, oscilloscope and/or bus analyzers.