Logic Designer for Processor Datapath Design Intern
Intel XNE Group's goal is to push innovation to make our products the highest performance and feature-rich Wireless Infrastructure Systems on the market. As an intern you will be working as part of our digital logic design and verification teams developing networking interface and switching technologies. You will be assisting with the digital logic design and/or pre-silicon verification of networking, high-speed interface functions & processing cores targeted at wireless access systems.
Your challenging responsibilities include:
- Working with senior engineers to implement digital Verilog RTL (register transfer logic) designs using Verilog programming and various digital design tools
- Develop System Verilog based verification models and tests to validate these designs
- Work with the team to debug and resolve complex design and verification problems as part of the overall development
- You may also participate in timing constraint, synthesis, and design audit work
- Participate with team members in the development of functional specifications, test plans, and work to debug simulation test failures
The ideal candidate enjoys working in a team environment and has a basic understanding of digital/RTL design and debug techniques. The position requires attention to detail, a willingness and ability to learn quickly, and excellent team communication skills. Candidate must have strong problem analysis skills.
Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
The candidate must be pursuing a Master’s or PhD in Computer Architecture and/or Electrical Engineering with emphasis in digital arithmetic and low power circuit design.
3+ months of experience in:
- Processor architecture, digital arithmetic, RTL design, verification, standard cell synthesis and place & route
- Verilog design, simulation, synthesis and P&R using industry standard tools
- Use of scripting languages such as TCL/Perl/Python
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