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CPU Physical Design Engineer

Austin, Texas, Estados Unidos| Hillsboro, Oregón, Estados Unidos| Phoenix, Arizona, Estados Unidos| Santa Clara, California, Estados Unidos| Fort Collins, Colorado, Estados Unidos| Hudson, Massachusetts, Estados Unidos ID de la oferta JR0259795 Categoría de Trabajo Silicon Hardware Engineering Modo de trabajo Híbrida Nivel de experiencia Experienced

Job Description

Role and Responsibilities:

Responsibilities for this CPU Physical Design Engineer will include but are not limited to:

  • Sets up APR flows for new process technologies and verifies PPA on new leading edge technologies and provides feedback to process team.
  • Expert with Synopsys Fusion compiler flows.
  • Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
  • Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  • Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  • Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
  • Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
  • Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
  • Optimizes CPU design to improve product level parameters such as power, frequency, and area.
  • Participates in the development and improvement of physical design methodologies and flow automation.

The ideal candidate should exhibit behavioral traits that indicate:

  • Excellent interpersonal skills, including written, verbal, and presentation communications.
  • Attention to detail and organizational skills.
  • Job involves dealing with ambiguous information and analyzing huge amounts of data.
  • To be successful in the job, the candidate should be able to work independently with little to no help.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

Candidate must possess a Master's degree in Electrical Engineering, Computer Engineering or similar degree and 4+ years' experience OR a PhD in Electrical Engineering, Computer Engineering or similar degree with 2+ years' experience.

  • 5+ years of hands-on experience in setting up Synopsys APR flows and converging designs in Fusion Compiler.
  • Expertise in Python, Perl, TCL is needed.

How to Stand out (Preferred Qualifications):

  • Intimate understanding of Fusion compiler and ability to set up APR flows is very much needed.
  • Experience with Cadence is a plus.
  • Debugging and documentation skills.
  • The team consists of 1 person only other than the manager. So hands-on experience is a must-have.

Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara; US, CO, Fort Collins; US, MA, Hudson

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, Colorado, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Posting End Date

The application window for this job posting is expected to end by 06/27/2024

Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

Siempre he querido hacer algo que cambie el mundo. En Intel, me siento apreciada y he ganado más confianza en mí misma. Me hacen sentir que soy capaz de lograr grandes cosas.
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