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Senior Power-Intent/ESD Engineer

San Jose, California; Hillsboro, Oregon; Austin, Texas; Phoenix, Arizona; Folsom, California; Santa Clara, California; Boulder, Colorado; Denver, Colorado; Arizona Job ID JR0238166 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description

As a Technical lead of the FPGA Full chip Global Power Intent team, you will be responsible for all aspects of Power Intent/ ESD verification for our next generation full chip product execution, as well as take an active role in next generation methodology development and flow enhancements.

Your scope in this role will include, but not limited to:

  • Power distribution network design and validation.

  • Provide Electrostatic Discharge (ESD) and latch up planning including Single Event Latchup (SEL) and signoff.

  • Perform IREM: power grid drop, Electro Migration (EM) spec definition and verification, physical and reliability collateral generation, and database management.

  • Power electrical and Design rule checking (ERC/ DRC).

  • System level power delivery analysis including power up and power down analysis.

  • Proficiency in tools, flows and methodology development needed to verify and debug.


Qualifications

Relevant experience can be obtained through work, classes, projects, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirement

Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

What You’ll Bring (Minimum Qualifications)

8+ years of relevant experience, experience should include:

  • ESD cell design and/or implementation and signoff in IP/SOC

Ways to Stand Out From the Crowd (Experience in one, or more, of the following preferred qualifications is considered a plus factor):

  • 12+ years of relevant experience.

  • Power distribution network design, IR/EM, ERC, Design Rule Check (DRC).

  • Verilog, Spice full custom and ASIC design flows. with 5 years experience

  • Analog design experience.

  • Experience with PERL/Python, TCL, Linux Shells.

  • Tool experience in any of the following : RedHawk, Totem, SeaHawk, RapidESD, Vortex, UPF, ERC, DRC.


Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US,OR,Hillsboro;US,TX,Austin;US,AZ,Phoenix;US,CA,Folsom;US,CA,Santa Clara;US,CO,Boulder;US,CO,Denver;US,AZ,Virtual


Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html


Annual Salary Range for jobs which could be performed in US, Colorado and New York:$139,480.00-$209,760.00
*Salary range dependent on a number of factors including location and experience

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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