Skip to main content
Search jobs

Product Development Engineer Lead

San José, Provincia de San José, Costa Rica Job ID JR0258199 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Experienced

Job Description

Leads development of testability and manufacturability activities for integrated circuits from the component feasibility stage through production ramp. Is an active participant in the design, development, and validation of testability circuits, test flows, and methodologies for new products through evaluation, development, and debug of complex test methods. Is able to understand new and complex requirements and lead a team that Interfaces with process development, fab, factory, assembly, quality and reliability, and manufacturing groups to enable post-silicon HVM ramp. Evaluates new designs on automatic test equipment (ATE) and works with the design, DFx, and product development teams to debug functionality and performance issues to root cause. Performs ATE device characterization, utilizes that data to define datasheet specifications and performs yield analysis. Collaborates with designers to drive design for test/debug/manufacturing (DFT/DFD/DFM) features enabling efficient production testing of new products. Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions. Tests, validates, modifies, and redesigns circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. Drives test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to both quality and cost constraints. Leads and drives manufacturing readiness from fab, assembly, and test factory to support engineering sample and customer sample generation (ES milestones), wafer start planning, product qual execution strategy and capacity analysis, and assembly and test site certification activities. Works with fab, assembly, and test factory partners and planners to support production ramp. Able to manage execution of new product introductions in the fab, fab process targeting, product/process optimizations, and participate in factory task forces to bring product perspective and respond to product issues. Optimizes product supply through data analysis of postsilicon binsplit, die level cherry pick (DLCP), and optimize sort/test content and yield downstream through data analysis.


  • Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

- Bachelor’s degree or MsC Degree in Electrical Engineering or related field with 6 years of related experience in test or test equipment to support debug and characterization of SOC/ASICs.

- At least 2 years of experience leading small teams of engineers coordinating tasks and interfacing with engineering teams across the globe.

- Candidate must have unrestricted permanent right to work in Costa Rica.

- Intermediate to Advanced English level

Preferable qualifications:

4 Years of experience in SoC tools/methodology ( VCS, Synthesis, Tessent Industry standard ATPG/MBIST tools design compiler etc.); or other test development tools.

Knowledge of programing languages such as C/C++ Perl/Python/TCL scripting.

4 Years Experience with hardware description languages such as Verilog and/or System Verilog and familiar with RTL design and micro-architecture.

Knowledge of Test Program development on High Volume Manufacturing (HVM) testers/ Platforms.

Knowledge of DFT architectures and methodologies in any of the following areas: Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan etc

Knowledge of Intel CPU/SOC or other ASIC architecture, scripting/programing and UNIX.4 Years of experience in project management of complex engineering activities.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

  • Architecture Technical Manager Petah Tikva, Israel View job
  • Senior Firmware Engineer Bengaluru, India View job
  • Technical Manager Multiple Locations View job
View all jobs

You don't have Recently Viewed Jobs yet.

View all jobs

You don't have Saved Jobs yet.

View all jobs