Skip to main content

SMTS SerDes Application Engineer

Malaysia Job ID JR0236422 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description
Job Description: As a member of Intel's Programmable Solutions Group, you will interface with architecture and design, and are responsible for validation/product engineering, ensuring best SERDES performance and the testability of the integrated circuits from the component feasibility stage to production ramp. The role provides exciting challenges of creating and implementing test/validation methodologies using the latest design-for-test (DFT)/BIST capabilities in different areas including SOC/Platform/System Test as well as automated test equipment. Structured ASIC team: This is a structured ASIC team under Intel's Programmable Solutions Group targeting 5G, cloud computing and high-end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC. Structured ASIC team in Intel's PSG group is the strategic acquisition of eASIC (the de facto leader in structured ASICs). Due to the proven success with our current and previous products (eASIC-N5X and eASIC-N3XS), we are building out our team to support the growth of new product families and rapidly expanding customer base. This success is an outcome of a close-knit integration of technologists across architecture, design and verification/validation, and deep customer engagement. Learn more about us: Responsibilities: � Provide hands-on applications leadership to internal and external customer programs pre and post silicon. Drive post-silicon validation, debug to root cause and provide resolution. � Develop collateral such as application note and device handbook/datasheet. � Define test methodology for high-speed SERDES (PMA and PCS), I/O, PLL, core logic block and influence the test chip design implementation and characterization/evaluation board design. � Work on improving validation/debug infrastructure including: Equipment automation, scripting. � Customer issue debug support. � Functional test vector generation and debugging.
Qualifications: You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Education Requirements: Bachelors' degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 15 plus years of experience or Masters' degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 10 plus years of experience. Minimum Qualifications: � SERDES architecture and protocols such as PCI-Express or 100GBASE-KR4, 25GBASE-KR or JESD204x or CPRI/OBSAI or DisplayPort or HDMI or CEI28. � Experience in signal integrity concepts, including sources and causes of noise and jitter and high-speed IO validation. � Communications system theory as it pertains to SERDES specifically, including PLL and clock data recovery (CDR). � Hands on experience with test equipment such as high-speed oscilloscope, BERT and VNA. � Good programming experience, preferably in Python. Preferred Qualifications: � Experience in FPGA eco system. � Test content generation and validation experience. � Fundamental knowledge of Design-For-Test requirements, including exposure to automated test equipment (ATE) tester platforms.
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

  • Senior Chipsets Logic Design Engineer Multiple Locations Apply Now
  • Senior DFT Engineer Malaysia Apply Now
  • CPU-SoC DFX Pre-Si Validation Engineer Multiple Locations Apply Now
View All Jobs

You don't have Recently Viewed Jobs yet.

View All Jobs

No jobs have been saved.

View All Jobs