PDK Development Engineer
Malaysia Job ID JR0240327 Job Category Software Engineering Work Mode Hybrid Experience Level Entry Level
Job DescriptionThe Process Design Kit (PDK) Development team within Design Enablement (DE) organization is looking for talented individuals to work in Runset, Extraction, or Custom Layout and architecture domain. At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on innovative technologies. As part of the DE/PDK group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools. As PDK Development Engineer, you will be responsible for, but not limited to the following: - Develop physical layout verification design rule checker (DRC), Layout vs Schematic (LVS), and RC extraction runsets using industry standard EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus). - Work with the process development teams at Intel to define specifications for DRC, LVS, and RC extraction runsets. - Perform detailed evaluation of tool run results to validate proper tool behavior and identify root cause for any discrepancies found. - Develop new extraction techniques to address upcoming technology features not yet handled in existing industry extraction tools and validates EDA solutions against models and measured data. - Develop ESD/LU rule decks based on Design Rule Manual (DRM) requirements. - Creating reliability ESD and LU design rules specifications. - L0 or development quality assurance of custom layout EDA technology files and/or primitive libraries and other custom collateral used by industry standard custom design and layout for various Intel process nodes. - Develop and enhance automation software and scripts for tool regression and collateral generation, including quality check. - Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification. - Coordinate development of technology features, develop QA plans, and drive test-cases development working with relevant stakeholders. - Help library teams at Intel with technology path finding activities. - Manage and resolve internal/external customer tickets as per guidelines. #DesignEnablement
QualificationsThe candidate must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork class research and or relevant previous job and or internship experiences. Minimum Qualifications: Bachelor/Master/PhD in Electrical Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field. 6+ months of work or educational experience in at least one of the following areas: - Unix/Linux operating system - Programming or scripting in at least one of: C++, Python, Ruby Perl, Tcl, SKILL - Layout of analog, RF, or digital circuits on advanced process technology nodes - CMOS device physics, process technology and design rules Preferred Qualifications: - Experience with working in software repository management tools like Git - Knowledge of DRC/LVS/Extraction runsets - Knowledge in semiconductor device physics, models, parasitic extraction, and technology scaling - Familiarity with VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures - Working knowledge of EDA tools (Synopsys ICV, Siemens/Mentor Calibre, Cadence Pegasus, Virtuoso or Custom Compiler, Cadence Innovus, Synopsys Fusion Compiler or Siemens Aprisa tools)
Inside this Business GroupAs the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Working ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie Offensive Security Researcher
“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”
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