Design Automation and Methodology Engineer (EDA)
It's an exciting time to join Intel in a leadership role as a Design Methodology and Automation Engineer for FPGA Design, with Intel's Programmable Solutions Group.
Performs as a highly proficient technical individual contributor in the space of Design Automation and Methodology - Custom Design Enablement and/or Physical Verification(PV).
Leadership responsibilities could include defining improved methodology and identify gaps for FPGA backend design activities from concept to implementation and support of EDA tools and flows, tool evaluations, etc.
Lead work groups with design teams to align on Custom Design Methodology and/or PV methodology, and help drive vendor tool updates.
Provides technical direction, guidance and support to the design team and stakeholders throughout the design life cycle on flows for quality release and tape-out.
Liaise with EDA vendor's and other internal DA teams for enablement, address bugs, enhancement request and support.
Work on Virtuoso construction capabilities (PDK, std cells, Pcells, Fill Flow) and/or PV runset/rule deck, submitter development and efficiency enhancements to improve turn-around-time with improvements on Quality.
Responsible in capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end-to-end testing of the software tools.
Liaise and consult on handoff flows and methodology from Custom to Structural Design to Fullchip teams.
Involved in developing the skills of less experienced engineers designers through formal training, coaching, or mentoring.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Master's/Bachelor's Degree in Electrical and Electronics Engineering, Computer Engineering, Microelectronics Engineering, or closely related field.
10 years of experience in the industry. Minimum of 5 years with Physical Design (Custom or ASIC) experience or Design Automation.
Experience with industry-based (CAD) layout tools including Cadence (Virtuoso, VXL, Skill scripting) and/or Synopsys (Custom Compiler).
Experience in Physical Verification (DRC, LVS, and others - on Synopsys ICV or/and Siemens Calibre SVRF/TVF/PERC coding.).
Familiar with backend IC design Tools, Flows and Methodologies and provide best suited coding to achieve intended functional goals.
Experience with the layout of standard cells for APR, custom standard cell library, PDK content and building runset regression test cases.
Experience in analog design and layout guidelines. Eg. matching devices, symmetrical layout, signal shielding, and other analog-specific guidelines will be an added advantage.
Experienced in TCL, Shell, perl, python scripting, and has interest or exposure in 3D IC design, Machine Learning and Artificial Intelligence will be an added advantage.
Experience in Layout floor-planning, power plan, routing plan, hierarchical layout assembly, custom cell design, optimized cell sharing, and final layout generation will be an added advantage.
Knowledge in advance technology nodes below 7nm will be an added advantage.
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