ASIC/FPGA Design Engineer

Job Description

• Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. 

• Participates in the definition of architecture and microarchitecture features of the block being designed. 

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. 

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. 

• Supports SoC customers to ensure high quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications

Qualifications

• Minimum qualifications are required to be initially considered for this position.

• Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog RTL coding.

Preferred Qualifications:

• Experience with Packet Based Protocols such as PCIe, SPI, I2C and etc is an advantage

• Demonstrable experience in logic design and writing RTL in Verilog or SystemVerilog

• Familiarity with a range of internal and 3rd-party logic design tools.

• Strong analytical ability, problem solving and communication skills

• Gate-level understanding of RTL and synthesis - i.e. understand how RTL looks like/behaves after it is synthesized into gates.

• Experience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issues.

• Strong communication and team-work stills.

• Ability to work independently and at various levels of abstraction

• Ability to lead a team of designer.

• Knowledge in FPGA design and debug with intel FPGA tools like Quartus will be an added advantage.

• Knowledge on embedded SW which using NIOS or ARM processor is an added advantage.

• Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.