Defect Control Engineer
Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.
As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in high-volume manufacturing at a 2-year cadence going forward.
Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.
This job requisition is to seek Defect Control engineering roles in FSM HVM Global Yield organization, reporting to Defect Control team manager.
Selected candidates will work with other members in Global Yield org including Process Integration, Yield Analysis and Device Integration teams, fab module/yield teams and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.
Defect Control engineers' responsibilities include (but not limited to):
Collaborate with Technology Development team and Process Integration team members to import and setup new technology to production fabs.
Work with Process Integration teams, Yield Analysis team and FSM Yield teams to ramp-up production yield in high-volume manufacturing phases.
Set up and optimize wafer inspection steps and recipes in process flow to ensure detection of yield detracting defects in line at step.
Execute production wafer inspection strategy to protect yield and quality at maximum productivity and lowest cost.
Build, maintain and update defect library per technology and per product.
Identify systematic defect issues and drive mitigation actions with Defect Reduction team in defined timeline to meet committed production yield targets.
Candidate should possess the following behavioral skills:
Problem-solving technique with strong self-initiative and self-learning capabilities.
Ability to work with multi-functional, multi-cultural teams.
Must demonstrate solid communication skills.
Bachelor's degree in science and engineering major.
Hands-on experience in advanced node semiconductor industry in Defect engineering or Failure analysis.
3+ years' experience in identifying defect mechanism, assessing its yield impact and improving D0.
3+ years' experience with defect inspection tools in high-volume semiconductor manufacturing.
3+ years' Hands-on experience in wafer inspection recipe setup and optimization.
3+ years' experience with layout-sensitive defects and knowledge of scan diagnosis and other defect analysis skills.
3+ years' experience working level understanding on Device Physics and experience in FinFET technology development or high-volume manufacturing.
Advanced degree (Master's or Ph.D.) in Physics or Materials Science major.
Experience in project/program management and/or TFT lead.
Demonstrated interpersonal skills including influencing, engaging, and motivating.
Experience in serving external Foundry customers through technical interactions.
Experience in GAA (Gate-All-Around) technology architecture and understanding on GAA-specific defect issues.
Experience in new semiconductor technology development.
Basic understanding and collaboration experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.