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Defect Reduction Engineer

Kiryat Gat, Southern District, Israel Job ID JR0247858 Job Category Manufacturing and Process Development Work Mode Hybrid Experience Level Experienced

Job Description

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany. As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in high-volume manufacturing at a 2-year cadence going forward.

Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek Defect Reduction engineering roles in FSM HVM Global Yield organization, reporting to Defect reduction team manager. Selected candidates will work with other members in Global Yield org including Process Integration, Yield Analysis and Device Integration teams, fab module/yield teams and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.

Defect Reduction engineers' responsibilities include (but not limited to):

  • Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.
  • Work with Process Integration teams, Yield Analysis team and FSM Yield teams to lead fast paced yield ramp-up in high-volume manufacturing phases.
  • Identify systematic defect issues in line and design mitigation actions in defined timeline to meet committed production yield targets.
  • Own engineering projects to eliminate systematic defect issues with Process Integration teams, Yield Analysis team, and Fab module teams.
  • Work with Defect Control team to execute production line inspection strategy to protect yield and quality at maximum productivity and lowest cost.
  • Engineering support for technical interactions with internal and external customers.
  • Candidate should possess the following behavioral skills:
  • Problem-solving technique with strong self-initiative and self-learning capabilities.
  • Ability to work with multi-functional, multi-cultural teams.
  • Must demonstrate solid communication skills.


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's degree in science and engineering major.
3+ years' experience in advanced node semiconductor industry in Defect engineering.
3+ years' experience in identifying defect mechanism, assessing its yield impact and improving D0.
3+ years' experience in FinFET technology development or high-volume manufacturing with hands-on knowledge of FinFET technology process flow to analyze systematic defect sources and set mitigation actions.
3+ years' experience in developing improvement projects at module level and collaborate with module teams to improve process for reduced defectivity and improved yield.
3+ years' experience in layout-sensitive defect weak points and how OPC works.
3+ years' experience with module tool impacts to defects, inline parametrics and yield through PM life while understanding upstream and downstream impacts to other tools

Preferred Qualifications:
Advanced degree (Master's or Ph.D.) in Physics or Materials Science major.
Experience in project/program management and/or TFT lead.
Demonstrated interpersonal skills including influencing, engaging, and motivating.
Experience in serving external Foundry customers through technical interactions.
Experience in GAA (Gate-All-Around) technology architecture and understanding on GAA-specific defect issues.
Basic understanding and collaboration experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

#MSO_SH #foundry

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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