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SoC Power Architect

Hudson, Massachusetts, United States| Austin, Texas, United States| Folsom, California, United States| Santa Clara, California, United States Job ID JR0258076 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Experienced
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Job Description


SoC Power Architect : The DGAI architecture group is focused on execution in strategic growth areas of GPU-accelerated AI for Intel. The group is chartered with delivering solutions for AI products in enterprise, and datacenter, as well as high-performance computing (HPC).
In this challenging and forward-looking role, we are looking for outstanding architects at multiple levels to contribute to the SoC architecture team responsible for delivering complex multi-die/2.5-3D high performance and low power GPU/AI/accelerator SoCs for supercompute, discrete graphics, edge compute, visual cloud and server spaces.

The successful candidate would be expected to:

  • Develop innovative and scalable solutions in the power, clocking, boot, thermal and reset domains across diverse workloads and product configurations.
  • Formulate scalable algorithms and proofs of solutions for limits management (power, thermal, current, VR, others), power management to achieve best in class PnP.
  • Comprehend the different layers of HW-SW interactions to create optimal architecture solutions and interfaces - from Drivers running on the Host to FW management across different SoC functions - suitable partitioning of responsibilities across different entities within the power management infrastructure.
  • Have a strong understanding and to align analysis of AI/HPC/inference/training/3D rendering/media analytics/concurrent workloads and data (pre and post-Si) to identify and create maximum opportunities of proportional computing - ability to comprehend system performance bottlenecks for latency analysis and implications to closed/open loop optimal system solutions for best in class PnP.
  • Take ownership and delivery of architectural documents and engagements with implementation teams (design, verification, emulation and post-Si) to realize the system solutions - Writes clear and detailed technical documentation, specifications, and/or feature descriptions for complex projects to guide users and/or customers to use or implement output.
  • Provide multilayered technical expertise for next generation initiatives.
  • Influence SoC architects to align the SOC power architecture and Power management to the capabilities of the platform power delivery architecture to deliver optimized power efficiency and performance.
  • Perform with ambiguity and being able to adapt to evolving product requirements that are typical in the early architectural definition phase of programs.
  • Lead and drive virtual teams of senior cross-domain engineers.
  • Communicate a product vision clearly to team members and key partners and inspire actions that lead to great product definitions.
  • Knowledge of secure boot, system address map and requirements for PCIE/CXL devices and configurations to develop scalable boot solutions across HW/SW interacting with security, memory and DFX architects
  • Experience formulating the right boot and power management solutions in collaboration with Product and Platform, power Delivery and SW architects as well as SoC, memory, security, RAS, debug architects.
  • Hands-on coding experience in Python, C++, MATLAB - able to model solutions and showcase the feasibility in pre-Si


Qualifications


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications:

  • Bachelor/master's degree in computer science/computer engineering or any STEM related degree.
  • Over 8+ years of SoC architecture experience in power management, boot, thermal, reset, clocking and adjoining areas.



Preferred qualifications:

  • Knowledge of Graphics and accelerator architecture is a plus.
  • Prior knowledge of PCIE and CXL protocols is a plus.
  • Hands on Post-Si debug experience
  • Die-to-die integration and advanced packaging experience is a plus.

Inside this Business Group


In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations



US, TX, Austin; US, CA, Folsom; US, CA, Santa Clara


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $186,760.00-$299,166.00
*Salary range dependent on a number of factors including location and experience


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
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Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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