About the Role:IFS Foundry Technology Engineering and Customer (FTEC) team is a critical team to lead Intel's design methodology and flow in advanced technology. As a role in IFS FTEC team, should be familiar with entire ASIC (APR) design flow and qualified to have design experience in ASIC (APR) design. In this position, the candidate will be responsible for the ASIC (APR) design methodology/flow development especially in the areas of synthesis, floorplan, PnR, Timing, ECO, and PG/EMIR design. As part of this role, the candidate is expected to work with various cross functional teams and external EDAs to oversee the execution all the way. The candidate is responsible to run PPA benchmarking, validate new design flow/methodology, and figure out the potential flow issue. In addition to the above, the candidate's ability to come up with a design solution is a plus. The selected candidate for the ASIC Design Methodology and Flow Development Engineer position will be responsible for but not limited to: Strong expertise in any one or multiple of the following areas: 1) Advanced ASIC (APR) design including Synthesis, Floorplan, PnR, PG/EMIR, Timing, and ECO; 2) ASIC (APR) design flow development and EDA tool certification; 3) Design Service; 4) EDA design tool and design automation Self-motivated and detail-oriented, capable of articulating complex concepts and solutions ; 5) EDA views development and qualification; 6) Qualification of PDK/reference flows/Foundation IP. Demonstrated design experiences to secure supports and working experiences with cross-functional teams in achieving goalsThe ideal candidate should exhibit the following behavioral traits: Coordination mindset with a focus on development design methodology and flowSkills with EDA ecosystem partnership collaborations
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:MS/Ph.D. degree in Electrical Engineering, Computer Science, or a related field of study 5+ years experiences in ASIC (APR) design, flow development, and EDA enablementTechnical background in EDA toolsProgramming skill: TCL or SKILLPreferred qualifications:Experience in PDK development is a plusEvidence of organizational and planning skills for engineering projectsGood communication and presentation skills to executive project coordinationExperience working with multiple function teams for EDA ecosystemAbility to set goals and objective with priorities, drive results across cross functional boundariesExcellent project control skills to prioritize the urgencies to meet schedule in an ambiguous environmentProgramming skill: Python or PERL or C++ or TCL
Inside this Business Group
Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
This role will require an on-site presence.