Senior Runset Development Engineer

Job Description

Your responsibilities will include, but are not limited to:

• Using Calibre, ICV and/or Pegasus verification languages to provide algorithmic solutions to resolve density deficiencies in physical design to meet manufacturability constraints.
• Working with users, process developers and design rule owners to develop requirements.
• Automating the development process to improve the efficiency, quality, and deployment.
• Design tests used to validate products and software tools at unit, and integration from end to end.

The ideal candidate will be expected to grow talent and have good verbal and written communication skills.

Qualifications

Minimum Education level with Experience:

• Bachelor in Electrical Engineering, Computer Engineering with 6+ years of semiconductor industry experience
• Masters in Electrical Engineering, Computer Engineering with 4+ years of semiconductor industry experience
• PhD in Electrical Engineering, Computer Engineering with 2+ years of semiconductor industry experience

Experience in the following areas:

• Design Rule Development using Calibre, ICV, or Pegasus tools (such as SVRF/TVF, PXL, PVL/PVTCL) with exposure to VLSI design and execution.
• Algorithmic development and translating rules into runsets.
• TCL and Python and Unix-Linux platforms.
• Developing test cases to validate runsets(DRC, LVS, antenna, density or fill modules)

Preferred Qualifications:

• Exposure to layout, schematic entry using Cadence Virtuoso and Synopsys Custom Designer
• Exposure to semiconductor device physics models and technology scaling
• Familiar with industry standard CAD tools flows for digital analog design

#designenablement

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US,TX,Austin;US,AZ,Phoenix;US,CA,Santa Clara

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html



Annual Salary Range for jobs which could be performed in US, California: $139,480.00-$209,760.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.