Skip to main content
Search jobs

Physical Design Engineer

Hillsboro, Oregon, United States Job ID JR0269480 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Entry Level Full/Part Time Full Time
Apply

Job Description


Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Want to learn more? Visit our YouTube Channel or the links below! 

Responsibilities include but not limited to:

  • Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

  • Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

  • Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

  • Analyzes results and makes recommendations to fix violations for current and future product architecture.

  • Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

  • Optimizes design to improve product level parameters such as power, frequency, and area.

  • Participates in the development and improvement of physical design methodologies and flow automation.


Qualifications


This is an entry level position and will be compensated accordingly.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.


Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering or any STEM related field with 1+ years of relevant experience or Masters degree in Electrical Engineering, Computer Engineering or any STEM related field.

Relevant experience should include the following:

Backend design and/or integration in any of the following areas:

  • Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.

  • Static timing analysis constraint understanding and generation, clock stamping, and timing closure.

  • Multiple Power Domain analysis using standard Power Formats UPF or CPF


Inside this Business Group


In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in the US $91,500.00-$137,436.00
*Salary range dependent on a number of factors including location and experience


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Apply
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

  • VP, Construction and Facilities Supply Chain (CFSC) General Manager Multiple Locations View job
  • Physical Design Engineer Hillsboro, Oregon View job
  • SOC Design Engineer San José, Costa Rica View job
View all jobs

You don't have Recently Viewed Jobs yet.

View all jobs

You don't have Saved Jobs yet.

View all jobs

Join Our Talent Community

Be the first to hear about what's happening at Intel! Sign up to receive the latest news and updates.

Sign up