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Logic Design and Pre-silicon Verification Engineer

Hillsboro, Oregon Job ID JR0239127 Job Category Engineering Work Mode Hybrid Experience Level Experienced

Job Description

As a member of the Logic Design and Validation group within the Lead Vehicle Development group in Design Enablement you will be part of a team that develops the RTL models and pre-silicon validation tests for test chips on the next generation Intel silicon manufacturing process.

Your responsibilities would include:

  • Creating new digital, analog, and mixed-signal RTL models for new and existing designs.
  • Running the Functional Equivalence Verification (FEV) flow to compare RTL to schematics.
  • Owning the creation of pre-silicon validation test plans, formal SystemVerilog/UVM testbenches, and validation test cases.
  • Owning RTL design of new digital systems ranging from design-for-test (DFT) on existing systems to novel designs to enable Power-Performance-Area (PPA) studies on next-generation technology nodes.

Candidate should exhibit the following behavioral traits:

  • Motivated, driven, with sense of urgency and commitment to achieve targeted goals.
  • Communication and problem-solving skills.
  • Documentation, and presentation skills.
  • Troubleshooting and analytical skills.



You must possess the below minimum qualifications to be initially considered for this position.

Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Candidate must possess a MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering, Computer Engineering or related fields.

3+ years of experience in any combination of the following:

  • Performing Pre-Silicon Logic Validation at Unit level or Integration level.
  • Digital design using Verilog and SystemVerilog.
  • Pre-silicon logic validation closure for multiple projects/designs.
  • OVM/UVM, preferably in testbench design and setup for reusability.
  • Defining overall validation approach for complex digital system and execution of those plans.
  • SystemVerilog Assertions (SVA), their creation and application in closing validation coverage.
  • Coverage-based verification and how to leverage for efficient validation closure.

Preferred Qualifications:

1+ years of experience in the following:

  • Analog circuits and their interaction with digital systems.
  • Unified Power Format (UPF) specification.
  • Scripting and automation with languages such as Perl or Python.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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