CAD /Software engineer
As an EDA Tools Software Engineer in the Lead Vehicle (Test Chip) Development group, you will be responsible for the development of physical design automation tools, flows, methodologies, and processes to support design of Intel's next generation process technology and yield test chips.
Your responsibilities will include, but not limited to:
- Development of EDA software tools and flows that automate generation of E-Test structure devices, routing, layout dummification, and physical design verification.
- Development of Design Rule Check (DRC) run-set software to implement test structure process design rules.
- Development and support of test chip layout library for the latest process nodes.
- Collaborating with semiconductor process technologists to define test structure designs.
- Troubleshoot design and DRC verification issues with complex physical design flows and tools.
About the team and organization:
Intel's Lead Vehicle Development (LVD) Team is one component of the larger Design Enablement (DE) organization, that provides design and manufacturing services to a variety of internal and external customers who leverage Intel's holistic design and manufacturing expertise to deliver unique circuits and systems at the leading edge of the technology curve. LVD's mission is to develop test-chips and other hardware prototypes that enable our customers to use Intel's most advanced process technologies to develop innovative products and reduce their time-to-market.
This is an entry level position and compensation will be given accordingly.
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your school work and/or classes and/or research and/or relevant previous job and/or internship experiences.
Candidate must possess an MS degree with 6+ months of experience or a PhD degree with 1+ years of experience with 1+ years of experience in Electrical Engineering (EE or ECE or ECSE), Computer Engineer, Computer Science, or related engineering discipline
Must have the required degree or expect the required degree by the date of start.
6+ months experience in the following:
- Programming and scripting languages such as Python, Tcl, or C++.
- UNIX/Linux computer platforms.
- Layout design rules, CMOS physical layout design, VLSI test circuits, device physics and semiconductor processing.
6+ months of experience in the following:
- Industry-standard EDA tools such as Cadence Virtuoso, Synopsys ICV, Siemens Calibre for use in physical design, place and route scripts, and DRC verification.
- Development of parameterized cells (PCells using Cadence SKILL) or PyCell.