Signal Integrity Engineer (Junior)
We are responsible for developing the platform interconnect design guidelines for State-of-the-art server platforms which support the latest processors and other server products.
In this position, you will be working with a team of Signal Integrity Engineers and will be developing interconnect interface solutions. Your scope of responsibilities will include, but are not limited to:
- Engaging with silicon designers platform, designers package, designers electrical, validation teams, and external customer support teams
- Performing modeling and simulation of highspeed IO (Input-Output) interconnect channels
- Developing package and platform design guidelines. Defining and evaluating circuit design features required to support interconnect performance requirements
- Creating signal measurement test plans and reviewing measurement results
- Correlating measurements to simulations
- Supporting signal integrity tool and methodology development
- Team player skills and willingness to learn
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
- Candidate must possess a Bachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, or related STEM field (documentation related to Bachelor's degree completion will be required)
- Intermediate to advanced English communication skills
- Signal Integrity experience supporting high-speed/low-speed signals and memory interfaces such as PCIe Ethernet DDR
- Fundamental knowledge of transmission line theory and high-speed/low-speed Printed Circuit Boards (PCB) design
- Experience with EDA Tools Mentor Graphics Cadence etc
- Experience with simulation tools MATLAB, HSpice, and ADS
- Knowledge of Intel Architecture
- Design of Experiments (DOE) and statistical knowledge and experience would be an added advantage
- Transmission line modeling using Field Solvers Ansoft 2D HFSS, Q3D, and CST electromagnetic simulator
- Lab equipment such as TDR VNA digital oscilloscopes and logic analyzers
- Experience with silicon device modeling methods such as IBISAMI or Verilog A
- PCB layout process and methodology.
- Experience using scripting languages (e.g. Python, PERL, etc.)
- Board-level system architecture basic silicon design IO structures and topologies.
- Understanding of electromagnetic concepts.