Sr. E-Core CPU Physical Design & Verification CAD Engineer – Transistor Level Flows

Job Description

Do you want to engineer the future? The E-core team is powered by some of the brightest and most innovative minds in the industry and we need more!

Role responsibilities include:

Your responsibilities in this highly visible role will include, but not be limited to:

• Defining, implementing and drive project execution by supporting the methodologies and EDA tools necessary to verify backend signoff flows using standard-cell based designs

• Work closely with Physical Designers to drive solutions in 1 or more of areas, including Static Timing Analysis (STA), Formal-Equivalence Checking, Electrical Rule Checks (ERC), Static Noise analysis, Active/Dynamic/Leakage Power Analysis, LVS, Power-Rail Integrity, Extraction or ECO

• Develops and tests Engineering Design Automation tools, creates flows/scripts to analyze and test design methodologies including driving new innovations to EDA tool vendors

• Develop custom optimized solutions to address design requirements for leading-edge process technologies

• Validate and drive continuous innovation of PDK technology, library files and other collaterals used for standard cell design, layout, and signoff with EDA CAD tools

• Proficiency in benchmarking QOR and provide design guidance for better power optimization and/or techniques for frequency improvement and/or tool runtime improvement

• Create flows/scripts to analyze, test and improve design methodologies, including through Machine Learning, and look for inefficiencies

• Contribute to the development of multidimensional designs involving the layout of complex integrated circuits

• Document and help with guidelines/specs

The ideal candidate should exhibit the following behavioral traits:

• Good inter-personal, clear communication and good teamwork skills

• A can-do attitude driven by research and thriving on challenges

• Self-motivator with strong problem solving skills

• Willing to handle multiple projects simultaneously and prioritize to project timelines

• Good communicator who can accurately perform a deep-dive to assess, and summarize issues to management

• Takes ownership to provide recommendations and drives solutions through to completion

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelor's degree in Electrical/Computer Engineering with 4+ years of experience - OR - a Master's degree in Electrical/Computer Engineering with 3+ years of experience - OR - a PhD in Electrical/Computer Engineering with 1+ years of experience in:

• Deep understanding of most, if not all  Physical Design and Verification Tools, Flows and Methods used in VLSI back-end custom-transistor based designs

• Expertise using industry standard Engineering Design Automation (EDA) VLSI tools from 1 or more of Synopsys, Cadence and/or Mentor Graphics in one of more of the following areas of: STA, Power, ECO, LVS, Power-rail integrity, Noise and/or ERC flows

• Deep understanding and experience of signoff aspects in STA for timing closure (OCV, constraints, parasitics), LVS, Static Power Analysis or Signal integrity analysis (Noise, SI-crosstalk)

• Familiar with digital custom circuit transistor-level designs and topologies including dynamic circuit techniques and memories as well as SPICE models and netlists

• Desire to deep-dive into timing paths, perform QOR difference analysis and identify key issues

• Expertise with Linux environments and basic shell scripting

• Expertise is a must in 1 or more scripting languages such as Python, Perl and/or Tcl

• Knowledge in standard-cell liberty format syntax and digital circuit device-level SPICE modelling

• Knowledge in standard formats from 1 or more of transistor-level netlist, standard parasitic formats and/or SDC constraints

• EDA tool Tcl API coding

• Experience with advanced programming data structures

Preferred Qualifications:

2+ years of experience in one or more of the following:

• Cadence Virtuoso and/or SKILL coding

• Leading/Mentoring junior team members or prior interns

• Machine-learning methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement

• Timing and power ECO techniques and implementation

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US,Hillsboro

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html