Implement bottoms-up elements of multi power domains, multi clock digital chip design including but not limited to synthesis, floor plan, clock tree synthesis and routing. Perform verification including RC extraction, static timing analysis and closure, layout verification - DRC, LVS, cross voltage domain verification and abstract views generation. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design
Inside this Business Group
Bs.c in electrical engineering or equivalent* 2-4 years in physical design implementation including synthesis, floor plan, clock tree synthesis, routing, timing optimization, LVS and DRC.* knowledge of synopsys implementation tools DC,ICC and verification tool advantage* knowledge of scripting and scripting capabilities an advantage
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
Israel, Haifa;Israel, Petah-Tikva