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Job ID: JR0045629
Job Category: Engineering
Primary Location: Munich, DE
Other Locations:
Job Type: Experienced Hire

Senior Design-for-Test Engineer (f/m)

Job Description

Design-for-Test plays a central role in the design effort of any complex SoC to ensure that high quality products can quickly be shipped to our customers. Design-for-Test hence interfaces with all disciplines throughout a project's life, and is involved from concept to silicon bring-up.

As a senior DFT engineer, you work across all dimensions of DFT: drafting and implementing DFT architectures, DFT verification, MBIST, scan synthesis, STA, structural and functional pattern generation, and bring-up support and pattern debug. You also help to grow the team through mentoring and collaboration; scale your knowledge through creation of documentation, specs, and guidelines; and develop and pilot new concepts and approaches. Typically, your responsibilities would either include end-to-end ownership of DFT for specific IPs or subsystems, or for a particular aspect of DFT for a complete SoC, like scan synthesis or MBIST.

Our team drives innovation in DFT from concept to silicon. We are a multinational team and cooperate and work with teams around the world and from different fields, e.g. system engineering, digital SoC, and analog/mixed-signal/RF IP design teams, layout and synthesis teams, and test engineering. We are always striving to improve our flows and processes, to be open and easy to work with, and to grow both as individuals and as a team.


Qualifications

Ideal candidate will have several years of experience in digital IC or SOC design with a focus on design-for-test Ideal candidate enables others through mentoring, cooperation, writing, and knowledge sharing In-depth experience with industry standard DfT practices, e.g. relating to JTAG, MBIST, scan and ATPG Experience in working with scan synthesis, compressed ATPG, MBIST, simulation, and debug tools Experience in working with adjacent teams, for example architecture, design, LPS, etc. to ensure correct implementation of DFT functionality Experience in working with test engineering on pattern bring-up and debug is a plus Experience in coordinating DFT efforts for a complex SoC is a plus Hands-on experience with automated test equipment ATE is a plus M.Sc. or equivalent in electrical engineering, computer science, or a related field Fluent English required, German is a plus

Inside this Business Group

Communication & Devices Group: The wireless revolution at Intel! We are one team - passionate engineers and technologists from diverse industry backgrounds working together to realize a world of connected computing. We are bringing the best ideas from the brightest minds to deliver future mobile experiences into the market. We are on the journey towards making Intel a wireless leader with exciting products for the Internet of Things, 5G and an opportunity to change the world with your work.

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