-Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
-Participates in the development of Architecture and Microarchitecture specifications for the Logic components.
-Provides IP integration support to SoC customers and represents RTL team.
We are looking for B. Eng or M. Eng in Electronics, Computer or Electrical Engineering graduates who have 6+ years of digital design exposure and experience.
We would like someone with:
-Expertise in microprocessors, computer system architecture and high speed design as well as producer consumer transactions.
-Proficiency in digital state machine architecture and logic design.
-Knowledgeable in techniques for low latency, multi-clock and multi-power domain designs.
-In depth exposure to Static Timing Analysis, timing convergence, synthesis, ECO Engineering Change Order implementation and associated Structural/Physical Design flows and activities.
-Protocol knowledge in I/O specifications such as USB2, USB3, SATA, PCIe.
-Knowledge in HVM, DFX, scan, JTAG is an added advantage.
-Working experience in verification and integration activities including but not limited to test plan development, test writing, debug, integration and familiar with verification methodologies such as OVM, UVM or VMM.
-Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows.
The candidate should also be:
-A fluent communicator in both verbal and written forms.
-An independent, motivated team player with leadership qualities.
-Able to drive/influence issue resolution and proficient in stakeholder management.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.