Graduate Intern - HW Logic Design

Santa Clara, California, United States Job ID JR0258463 Job Category Intern/Student Work Mode Hybrid Experience Level Intern Full/Part Time Full Time

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Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Do you want to collaborate with the best minds in the world? Are you passionate about working with fabric designs that are integral to most silicon chipsthat Intel builds and also outside? Come intern with our team this summer.

Who You Are

In this graduate internship you will be working alongside a world-class IP design team within the DEGdelivering on next-generation Intel Products, be it Client, Server, AI, IOT.

Your responsibilities will include but are not limited to:

Design, documentation, and integration of design.
Logic design using Verilog and VCS.
Ensuring the logical design of block satisfies the architectural specification as well as protocol specification.
Generating focused and random test cases, analyzing coverage, and debugging failure cases

In addition to the qualifications listed below, the ideal candidate will also have the following:

Excellent communication skills
Teamwork skills
Strong analytical and problem-solving skills
Willingness to work independently and at various levels of abstraction.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork / classes / research and / or relevant previous job and / or internship experiences.

Minimum Qualifications:

Candidate must be pursuing a Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

6+ months of coursework in:

Digital design
Computer architecture

Preferred Qualifications:

Verilog and System Verilog
Scripting languages such as Python or Perl

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, California: $63,000.00-$166,000.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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