Design Automation and Methodology Graduate Intern

Santa Clara, California, United States| Hillsboro, Oregon, United States| Austin, Texas, United States| Phoenix, Arizona, United States| Folsom, California, United States| Fort Collins, Colorado, United States Job ID JR0258464 Job Category Intern/Student Work Mode Hybrid Experience Level Intern Full/Part Time Full Time

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Job Description

Role and Responsibilities:

In this role, responsibilities include (but are not limited to):

Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies. Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes. Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation.

Candidate should be a team player with proven skills at setting and meeting goals, and should possess strong written and verbal communication skills for interacting within team and with partner teams.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Currently pursuing a Master's, or PhD degree in Computer Science or a related field.

Excellent coding skills (Python, Tcl, Perl) and shell scripting.
Knowledge of data structures and graph algorithms and its application to electronic design automation (EDA) tools.
Experience with Revision control / automated build and test experience (Git, Makefiles, etc)

Preferred Qualifications:

Experience working on High Speed Interconnects.
UVM based test bench development and debugging is a definite plus

Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, OR, Hillsboro; US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CO, Fort Collins

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, Colorado, California:
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Posting End Date

The application window for this job posting is expected to end by 07/24/2024

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