Defect Reduction Development Engineer

Hsinchu, Taiwan, Taiwan Job ID JR0256194 Job Category Manufacturing and Process Development Work Mode Hybrid Experience Level Experienced

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Job Description

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany. As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in High-Volume Manufacturing (HVM) at a 2-year cadence going forward. Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek for Defect Metro Development engineering roles in FSM HVM Global Yield organization, reporting to Defect Metro Engineering Development manager. Selected candidates will work with other members in defect metro team, other teams in Global Yield org, fab module, yield, integration and TD team members to achieve yield ramp-up and defect reduction in early production stage, supporting internal and external customers.

Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.

Identify critical yield limiting defect steps and work with Defect Control team to set production line inspection strategy to protect yield and quality at maximum productivity and lowest cost.

Candidate should possess the following behavioral skills:

Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.
Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.
Proven track record of working across organization through matrix structures to accomplish strategic objectives with conflicting priorities.
Must demonstrate strong communication skills.

Qualifications

(*Job grade will be determined based on applicants’ experience level and qualification)

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in science and engineering major, with at least 10+ years of experience.
Strong understanding on defect mechanism and yield impact in semiconductor high-volume production and proven quantified track record of driving down D0.
8+ years of experience in advanced node semiconductor industry in Defect engineering.
Basic understanding and collaboration experience with processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.
Experience in Statistics and Machine Learning preferred.
Experience in working with Process Integration, Design and OPC teams to identify layout-sensitive defect weak points and address systematic defect issues.
Knowledge of module tool impacts to defects, inline parametric and yield through PM life while understanding upstream and downstream impacts to other tools
Experience in FinFET technology development or high-volume manufacturing with hands-on knowledge of FinFET technology process flow to analyse systematic defect sources and set mitigation actions.
Working knowledge in module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology. Skills to develop improvement projects at module level to improve process for reduced defectivity and improved yield.

Preferred Qualifications:

Advanced degree (Master’s or Ph.D.) in Electrical Engineering, Physics, Chemistry or Materials Science major is preferred, with at least 12-15 years of experience.
Experience in project/program management and/or Task Force Team lead.
Must demonstrate solid communication skills.
Ability to work with multi-functional, multi-cultural teams.
Demonstrated interpersonal skills including influencing, engaging, and motivating.
Problem-solving technique with strong self-initiative and self-learning capabilities.
Ability to leverage big data analysis to identify process design weaknesses and/or manufacturing weaknesses to propose corrective, data-based solutions.
Ability to extracts insights from structured and unstructured data by quickly synthesizing large volumes of data and applying statistics and machine learning.
Experience in new semiconductor technology development.
Experience in serving external Foundry customers through technical interactions.
Experience in GAA (Gate-All-Around) technology architecture.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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