Analog layout design engineer

Job Description

Designs complex layouts of analog signal circuits for a given design specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts. Designs and analyzes floorplans, power grid, ESD, bumps, and performs all required verification on the analog blocks. Performs the microfloor planning and detail signal planning of complex analog circuits to meet performance and electrical requirements (shielding, matching) for critical signals to optimize for area, power, RV, and performance. Develops and drives new and innovative analog layout methodologies to improve layout productivity and quality. Collaborates with analog circuit design, process technology, and package design teams to meet design specifications, plan work, and negotiate layout tradeoffs as needed. Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology used in analog layout design.

Qualifications

2 years Experience in analog layout Academic Qualification: -------------------------- M.Tech in VLSI design / B.Tech in EC Additional qualification: --------------------------- -Good knowledge on CMOS device physics. -Understanding of basic circuit and layout blocks in deep sub-micron CMOS/FinFET technology. -Exposure to basic analog layout blocks in Cadence Virtuoso tool environment, exposure to Synopsys Custom complier tool environment is plus.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


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Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.