Join a logic design team in the Client Development Group (CDG) Memory cluster. The team owns and delivers IPs to the latest Intel CPU SoC products including the recently released CofeeLake platform and future products in development. The team is specialized in memory management including various levels of caches andmemory controllers. As a logic design engineer you will contribute to specifications at the micro-architecture level. You will be required to implement logic design block andIntegrate logic functions required by the IP in System Verilog. Work will include collaboration with cross discipline stake holders including DFx design, pre silicon validation BE design teams and IP integration support to SoC customer
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.