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Job ID: JR0054290
Job Category: Engineering Management
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Design-for-Test Manager

Job Description

Our global team drives innovation in DFT from concept to silicon. We are a multi-national team and cooperate and work with teams around the world and from different fields, e.g. system engineering, digital SoC and analog/mixed-signal/RF IP design teams, layout and synthesis teams, and test engineering. We are always striving to improve our flows and processes, to be open and easy to work with, and to grow both as individuals and as a team.

Design-for-Test plays a central role in the design effort of any complex SoC to ensure that high quality products can quickly be shipped to our customers. Design-for-Test interfaces with all disciplines throughout a project's life, and is involved from concept to silicon bring-up. The a DFT Manager is responsible for leading a team responsible for providing an end-to-end design-for-test solution for IPs and complex subsystems that are central to Intel's mobile communication products. 

Responsibilities will include (but no tlimited to):
•    Cooperating with and influencing adjacent teams to find design-for-test solutions that best benefit our products. 
•    Growing the team and its members, supporting and encouraging continuous improvement and best practices. 
•    Establishing the team as a trusted and easy-to-work with partner for both our global DFT teams as well as local design teams.


Qualifications

Required Skills/Experience

  • BS or Equivalent in Electrical Engineering, Computer Science, or other related field
  • Prior experience (7+ years with a BS Degree OR 5+ with a Masters Degree) in digital IC or SOC design (preferably with a focus on design-for-test)
  • Understanding of design work flows, processes, and technologies and their impact on productivity and quality
  • Prior experience with industry standard DfT practices, e.g. relating to JTAG, MBIST, scan and ATPG
  • Experience in working with synthesis, compressed ATPG, MBIST, simulation, and debug tools-
  • Prior experience in cooperating with adjacent teams architecture, design, physical design, etc. to ensure good overall solutions

Preferred Experience/Skills

  • Prior experience in working in or with test engineering
  • Experience wtih focus on design-for-test
  • Prior experience in coordinating or leading design efforts for DFT or a comparable aspect of a complex SoC or subsystem
  • Previous experience in working in or with test engineering

Inside this Business Group

Communication & Devices Group: The wireless revolution at Intel! We are one team - passionate engineers and technologists from diverse industry backgrounds working together to realize a world of connected computing. We are bringing the best ideas from the brightest minds to deliver future mobile experiences into the market. We are on the journey towards making Intel a wireless leader with exciting products for the Internet of Things, 5G and an opportunity to change the world with your work.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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