The Scalable Performance CPU Development Group SDG is looking for energetic and passionate senior Verification Technical Lead for high speed serial link digital IP/subSystem.Expertize in OVM/UVM methodology with strong system-Verilog/System-C/OOPs know how. Experience in developing complex protocol monitors, checkers, scoreboard & coverage is highly desired.- Domain experience of high speed serial links specially PCIe and coherency protocols is needed. Understanding of global flow like DFT/DFD/Power management etc is added advantage.- Responsibility includes defining testbench architecture and executing overall testplan to achieve first time production worthy quality of the IP/Subsystem.- In this role, you will be required to interact with various stake holders to achieve end to end goals. You will also be responsible to mentor/coach some of the junior verification engineers working in the team.
Candidate should possess a Bachelor's degree with 12-17 years' experience or a Master's degree with 10-15 years' experience in VLSI, Electronics, Electrical, Computer Engineering or Computer Science from reputed colleges like IIT/NIT, global universities.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.