Job Description This is a senior layout technical leadership position. Candidate has to be strong in physical verification concepts and must have worked on layout verification activities on at least couple of major projects. Prior experience working on Intel process design rules will be a big advantage. You will be providing technical support to a team of employees that will be working on all the physical verification of digital blocks of a project that are constructed using Automated Place & Route flow. You will be required to provide technical support to the team on the day to day layout related issues, engage early with design team and provide feedback to designers on the layout quality of the blocks, review the blocks for readiness before they are handed for layout verification, develop scripts to improve the layout cleanup efficiency, send periodic status updates to upper management on the work status. You may also be required to handle the physical verification of complex blocks on your own.
Minimum B.E/B.Tech with 2+ year experience in using Synopsys ICC2 tool for layout verificationStrong scripting skills in any scripting languages like Tcl, Perl.Good communication and listening skills.Working knowledge on RTL-GDS2 flows.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.