Job Description Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
Qualifications required-Must have either a BS or MS in Electrical Engineering or Computer Engineering. -Minimum -5 years of experience in VLSI design or ASIC/SOC design experiences including synthesis, floor-planning, clock tree synthesis CTS, APR, static timing analysis, DRC/LVS, FV. -Knowledge of CMOS layout concepts-Experience in UNIX operating system, scripting languages such as PERL, TCL.-Experience with industry-standard IC CAD tools such as Synopsys DC, ICC/ICCII and ICV based layout verification flows is desirable-Circuit/physical design -experiences in the high performance and ultra-low power IC designs is a plus.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.