Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
BS or MS with 12+ years of experience in ASIC Physical Design. Strong expertise in high frequency clocking methodologies including global clock tree design and block level clock tree synthesis. Well versed with challenges with clock distribution in big System on chip and implementation strategies to address the same. Well versed with floorplanning, timing constraints, STA and timing closure. Experience with low power design features and flows.Working experience with tools like ICC, Primetime etc used in the RTL2GDSII implementation and spice simulation tools. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Strong analytical & Problem solving skills. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation for customer support.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.