Job Description Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.
Minimum Qualifications: Education : MS + 8 years or BS + 10 years relevant experience Major in Electrical Engineering or Computer Engineering Experience Knowledge and working experience of industry standard flows for Verilog, System Verilog RTL UPF based power methodology, etc. Automation skill and Proficiency in scripting languages such as Perl/Tcl Ability to multi-task and flexibility to work in a global environment Strong communication skills and have self-motivation. Strong analytical & Problem solving skills
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.