Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.To develop pre-silicon IP verification Test Bench environment using OVM/UVM methodology to validate SIP/HIP as part of sandbox and later as soc integration environment. Develop test bench environment to enable coverage, monitors and test feature set such as redundancy, ECC checks and deliver IP verification test sequences, which will scalable and portable to SoC environment. To enable Multiple Instances Of IP's into SoC test bench environment and support SoC to address SIP/HIP Soft/Hard IP related integration, arch issues. Adept in programming and/or scripting C++, Perl* and be conversant with flows and tools for VLSI logic design and/or functional verification.
Minimum Qualifications: Education : MS + 10 years or BS + 12 years relevant experience Major in Electrical Engineering or Computer Engineering Experience Knowledge and working experience of industry standard flows for RTL UPF based power methodology, etc. Automation skill and Proficiency in scripting languages such as Perl/Tcl Ability to multi-task and flexibility to work in a global environment Strong communication skills and have self-motivation. Strong analytical & Problem solving skills.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.