Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.
Education qualification with MS 10-12 years/ BS 14-16 years. Major in Electrical Engineering or Computer Engineering. Knowledge and working experience of industry standard flows for RTL to Silicon physical Design/ Verification e.g. ICC, Primetime is must. Understanding of structural design techniques/ methodology flows related to synthesis, place & route, CTS, timing convergence, layouts, UPF power methodology, OASIS/GDS file usage etc is also needed. Automation skill and Proficiency in scripting languages such as Perl/Tcl Ability to multi-task and flexibility to work in a global environment Strong communication skills and have self-motivation. Strong analytical & Problem solving skills.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.