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Job ID: JR0055129
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Staff Engineer - Physical Design

Job Description
Lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, LEC, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires extensive knowledge and practical application of methodologies and physical design. Intel CHD group develops Broadband Communication Technologies & Semiconductor solutions for modems for networks and digital homes. Advance SoC system-on-chip solutions address a wide variety of technologies, including GPON, xDSL/G,fast modems, WLAN Access Points, DOCSIS cable modems and being a significant supplier of access network integrated circuits. The group core expertise is to combine world-class mixed signal and digital signal processing to deliver Innovative system-on-chip integration. The activities at CHD India span from algorithm modelling, Architecture definition, specification development of the IC and system who owning world-wide responsibility of the Chip development, Firmware architecture, firmware development, Software architecture Software development and Customer Support. Solutions enable global system manufacturers to gain a commercial edge and create high-speed data and communication products which drive innovation in this market and deliver value to carriers and operators.


BE/BTECH/MTECH with 10+ years of experience in ASIC Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC/ICC2, Primetime etc used in the RTL2GDSII implementation. Strong knowledge and experience in standard place and route flows ICC2/Synopsys flows preferred. Well versed with timing constraints, STA and timing closure. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation for customer support. Strong analytical & Problem solving skills.

Inside this Business Group

The Client Computing Group is responsible for all aspects of the client computing business across Phone, Phablet, Tablet and PC platforms, leading Intel's efforts to transform client computing through technologies, new form factors, and driving Intel's corporate-wide user experience initiatives. This spans all client device brands including hardware, software and connectivity ingredients for phones, tablets, Ultrabook™, All-in-Ones, 2 in 1 computing devices, and home gateways.

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