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Job ID: JR0053835
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Colorado, Fort Collins;US, Massachusetts, Hudson;US, Oregon, Hillsboro
Job Type: Experienced Hire

Server Debug Architect

Job Description

About the team:

The Server Chassis Design for Debug (DFD) is developing debug capabilities for majority of Intel's server products. These capabilities are ranging from defining the product debug specification, through development of the debug IP's and fabrics, all the way to providing IP level support, automated fabric creation, automated verification tools and reference simplified functional SOC model with validation content enabled.

DFD s a set of global features incorporated in Intel server SOC's with purpose of enabling debug and optimization of server products on the platform level.

DFD features are coming into play in almost any aspect of the post-silicon phase and providing: reset and power management flows debug-ability, visibility into internal busses and states, ability to identify events of interest and taking actions bassed off these, collecting data for software optimization and more.

As a DFD Architect on SDG's chassis DFD team, you would work on:

  • Analysis, interpretation and assessment of hardware architectural specifications of functional logic, tailoring the DFD architecture for SOC's based on that using standard IP's and capabilities or new ones
  • Definition and development of microarchitecture specifications for debug blocks where implementations must meet functional and performance requirements, physical/structural design constraints, security standards, as well as proprietary design rules and other quality criteria.
  • Drive design reviews, verify that the DFD IP's and fabrics are being instantiated properly, understand the nuances and implication on debug use-cases and in the system level
  • Be a player in Intel debug community, represent the server's stance in various directions being investigated, improve debug architecture based on silicon debug learning, debuggers, and debug tools needs
  • Use your problem solving skills and think out of the box when required to solve complex problems and bugs, deliver in a timely manner.


Minimum Qualifications:

  • BS or MS Degree in Electrical Engineering, Computer Engineering, or related degrees
  • Excellent knowledge of ASIC/RTL/Logic design and verification methodology, 9+ years of experience in SOC design and post-silicon
  • Ability to review and assess quality of logic design, timing, CDC and reset
  • Deep knowledge of logic design quality tools like SpyGlass, Lint, etc.
  • Ability to absorb and ramp up quickly on huge amount of information
  • Good team work ability, be able to get the support you need and provide support for others, ability to communicate effectively with team members overseas
  • Good communications skills, report back status and raise flags where needed
  • Excellent problem solving skills, self-learner and fast performer, innovative and able to motivate others

Preferred Qualification:

  • System debug knowledge- an advantage
  • Intel served DFD architecture knowledge - an advantage.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, Colorado, Fort Collins;US, Massachusetts, Hudson;US, Oregon, Hillsboro

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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