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Job ID: JR0054223
Job Category: Engineering
Primary Location: Hudson, MA US
Other Locations:
Job Type: Experienced Hire

Engineering Manager

Job Description

This is an excellent opportunity to be part of Scalable Performance CPU Development Group SDG team doing exciting work in the development of next generation server Xeon microprocessors.

As a manager, you have to set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance. Also oversee definition, design, verification, support and documentation for IPs under your management.


Qualifications

Minimum Qualifications:

  • BS or MS in Electrical or Computer Engineering
  • 5+ years of design and/or validation experience in FPGA, ASIC or custom IC designs
  • 2+ years of leading and/or managing a design and/or validation team
  • Strong understanding of hardware design frontend and backend interactions and verification test bench architecture, test case development, functional coverage, coverage collection and analysis and how they apply to complex IP blocks
  • Good understanding of SoC design/validation practices and methodologies
  • Demonstrated ability to create and document plans
  • Demonstrated natural leadership abilities, being able to influence and inspire cross-functional teams and influence senior leadership
  • Exceptional communication skills both in written and in verbal form which are imperative in this collaborative capacity, which will play a highly significant role in determining how efficiently cross-functional duties are executed
  • Customer and result oriented, highly organized, highly analytical and procedural, and a creative and strategic thinker, and be able to work on multiple projects, adapt to changing priorities and meet tight deadlines
  • Insatiable thirst to learn and develop, work comfortably in a cross-functional environment and demonstrate an ability to stay calm in the face of uncertainty and stress

Preferred Qualifications:

  • Strong background in System Verilog, UVM and other programming environments
  • Experience with formal verification methods property checking
  • Experience in leading frontend activities including frontend integration or validation
  • Familiarity with Lean and Agile practices that include establishing processes for agile practices, including backlog management, sprint processes, user-story build-out, and product reporting

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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