Job Description The candidate will be part of graphics DFX team under Visual Technologies Teams VTT responsible for delivery of DFX features and scan test content for graphics IPs developed for Intel's CPUs/ SOCs . In this position, the candidate will primarily work on DFT design/implementation and/or ATPG for Intel's next generation graphics cores. Responsibilities include but not limited to:1.ATPG , DRC analysis , coverage-analysis .2.Validation of scan content through gate-level simulation .3.Work with structural design teams for ATPG input collaterals, timing closure and coverage improvement.4.Development of scan content generation/validation flows .5.Support post-silicon validation teams for content enablement on ATE & yield-improvement
Must possess a minimum of a BS or MS in Electrical Engineering with at least 3-4 years of hands-on experience in DFX. Strong knowledge of DFT architectures & methodologies. This includes Scan, ATPG, Mbist, BScan, IO DFx etc. Strong debug/problem-solving and communication skills. Ability to effectively work with cross-geo/functional teams. Strong knowledge of DFX tools/methodology such as Synthesis, Spyglass, ATPG/MBIST tools, design compiler, etc . Exposure to graphics / media architecture will be an advantage .Advanced Unix scripting and programming in C*/C++* or Perl/ TCL*. Strong logic design skills and experience in System Verilog / Verilog / VHDL desired.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.