Job Description Develops and supports digital circuit design for cell libraries. Performs custom digital circuit design and simulation. Designs, develops, modifies and evaluates digital electronic parts, components or integrated circuitry for use in digital electronic equipment and other hardware systems. Determines design approaches and parameters. Performs digital circuit design, verification and layout, data path design and digital block synthesis.
Mtech/Btech with 8+ years of experience in design or methodology development or EDA automation in the areas of design planning, Power network planning PNS, Clock tree design, timing budgeting and layout finishing in advanced process nodes. Focused effort on the PPA optimization working closely with the RTL, Layout & Signoff teams is desired. Expertise in the design Prior experience in lower power design concepts using IEEE 1801 UPF is an added plus. Team player, with good problem solving and communication skills is desired. Automation skills in PERL and/or TCL and/or Shell* is an added plus.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.