Job Description Responsibilities include but not limited to: Develop, improvise and deploy design methodologies & automation in the areas of low power design, implementation and verification of large Sub-Chips and Hard IPs designed in advanced Intel processes 14nm, 10nm or below. In this role the person will also be responsible to work with the design teams closely in the APAC GEO to enable the best in class low power design of these big sub-systems that gets integrated into various SoCs. He/she will get in depth expertise in the low power methods deployed in large designs like GFX, Imaging processors, Peripheral subsystems like PCIe, TypeC, Display, Media etc or other critical designs like Memory subsystems/DDR Gen5/6 and enable the best in class PPA out of these designs.
Mtech/Btech with more than 8 years of experience in design or methodology development or EDA automation in the areas of low power design, implementation, signoff & optimization techniques in advanced process nodes. Prior experience in PPA optimization and implementation by working closely with the RTL, Layout & Platform is required. Hands on experience in lower power design concepts implemented using IEEE 1801 UPF is required. Team player, with good problem solving and communication skills is desired. Automation skills in PERL and/or TCL and/or Shell* is an added plus.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.