Responsibilities include but not limited to: Design, development and signoff of complex clocking delivery networks of large Sub-Chips and Hard IPs designed in advanced Intel processes 14nm, 10nm or below. In this role the person will also be responsible to work with the design teams closely in the APAC GEO to enable the best in class design of big sub-systems that gets integrated seamlessly into the SoC clock delivery. He/she will get in depth expertise in handling large designs like GFX, Imaging processors, Peripheral subsystems like PCIe, TypeC, Display, Media etc or other high speed designs like Memory subsystems/DDR Gen5/6.
Mtech/Btech in the fields of computer engineering/science with 5+ years of experience in the areas of RTL2GDSII implementation Floorplanning, Physical design, APR and signoff flows of chip level or block level layouts in advanced process nodes. In-depth knowledge in advanced clock tree design like global clocks, HCTS, Fishbone, Multi Source CTS and optimization of the clock delivery for meeting power & performance of the high speed multi million gate designs is required. Prior knowledge in low power design using UPF 1801 is an added plus. Team player, with good problem solving and communication skills. Automation skills in PERL and/or TCL and/or Shell* is an added plus.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.