Job Description Responsible for delivering IP and Sub-IP blocks for critical Graphics products on leading edge process technologies using the latest design methodologies. Responsibilities will include but not limited to: Driving the Physical Design convergence on RTL 2 GDS multiple sub-IP and IP blocks. Understanding, validating and deploying new tools and solutions in multiple Digital VLSI domain like FEV, Timing, Place and Route, Analyze, debug and develop solutions for convergence challenges to meet design metrics like area, power and performance.
A Bachelor or Masters of Engineering degree in Electrical/ Electronic Engineering/ VLSI Engineering. 6 or more years of hands-on experience in physical design convergence from logic synthesis to layout verification. Knowledge of few of Industry standard EDA tool like Design Complier, Descartes, ICC, ICC2, Primetime, Red hawk and Formality Excellent understanding of digital design and circuit theory. Expertise in scripting languages like Perl and/or Tcl.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.