Job Description Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
Should possess a Bachaleors degree in Electrical Engineering with team leading experience. Additional qualifications include: Experience in ASIC Physical Design RTL to GDSII Implementation flow Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc. Experience with Low power design closure UPF based implementation and associated sign-off SG-LP/VCLP/Conformal Knowledge of Timing .lib generation, Physical View Generation LEF, GDS, CEL, FRAM, NDM etc. Physical Verification DRC/LVS/Density/Antenna etc. Reliability Verification EM/IR drop etc. Well versed with TCL/Perl/Shell Scripting EDA tool knowledge: Design Compiler, ICC/ICC2, StarRC-XT, Primetime, ICVGood communication and organizational skills Excellent Team work and customer orientation skills
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.