Job Description In a fast paced leading edge environment with endless possibilities of innovating and learning, you will be responsible for providing clocking solutions at partition CTMESH, CTS as well as sub-system Global level. Key responsibilities include but not limited toWorking closely with the design teams to define low power clock implementation strategyDefining new clocking methodology and algorithm that ensures low clock power at IP levelClock Skew Estimation and Budgeting strategyClock Circuit Design workClock Simulations using dynamic toolsEnsuring Clock quality through robust verification and sign off techniquesHe/she will get in depth expertise in handling large designs like GFX, Imaging processors, Peripheral subsystems like PCIe, TypeC, Display, Media etc or other high speed designs like Memory subsystems/DDR Gen5/6.
Mtech/Btech in the fields of computer engineering/science with more than 7 years of experience in the areas of RTL2GDSII Floorplanning, Physical design, APR and signoff flows designing chip level or block level layouts in advanced process nodes. Indepth knowledge in advanced clock tree design like global clocks, HCTS, Multi Source CTS and optimization of the clock delivery for meeting power & performance of the high speed multi million gate designs is required. Prior knowledge in low power design using UPF 1801 based flows is an added plus. Team player, with good problem solving and communication skills. Automation skills in PERL and/or TCL and/or Shell* is an added plus.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.