Apply Now    
Job ID: JR0053068
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Colorado, Fort Collins;US, Oregon, Hillsboro
Job Type: Experienced Hire

Server Debug Micro Architect

Job Description

About the team:

The Server Chassis DFD (Design for Debug) is developing debug capabilities for majority of Intel's server products, these capabilities are spanning from defining the product debug HAS, through development of the debug IP's and fabrics, all the way to providing IP level support. Automated validation tools and reference validation content on a simplified SOC model.

DFD is a set of global features incorporated in Intel server SOC's with purpose of enabling debug and optimization of server products on the platform level. DFD features are coming into play in almost any aspect of the post-silicon phase and providing: reset and power management flows debug-ability, visibility into internal busses and logic, identifying events of interest and taking actions basses off them, collecting data for software optimization and more.

As DFD Architect and Micro-Architect in SDG's chassis DFD team you would work on:

  • Analysis, interpretation and assessment of hardware architectural specifications of functional logic.- Definition of DFD architecture for SOC's and in the system level
  • Definition and development of microarchitecture specifications, logic designs, and HDL code for debug blocks where design implementations must meet functional and performance requirements, physical/structural design constraints, as well as proprietary design rules and other quality criteria
  • Integrate IP's into, fix bug in, and maintain the chassis CTE reference model
  • Interact with and support other logic designers who are consuming DFD flows and IP's as well as logic validators, structural designers and post silicon team
  • Use your problem solving skills and think out of the box when required to solve complex problems and bugs, deliver in a timely manner


Qualifications

Minimum Qualifications:

  • BS or MS Degree in Electrical Engineering or Computer Engineering with at least 5 years of relevant experience
  • Excellent knowledge of ASIC, RTL, and/or Logic design and verification methodologies
  • Proven track record of delivering complex ASIC/SoC successfully, as designer or validator
  • Good team work ability, be able to get the support you need and provide support for others.
  • Good communications skills, report back status and raise flags where needed
  • Excellent problem solving skills, self-learner and fast performer, innovative and able to drive others

Preferred Qualifications:

  • DFD/DFT knowledge- an advantage

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.



Other Locations

US, Colorado, Fort Collins;US, Oregon, Hillsboro


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Apply Now    

What would you like to do now?

Connect with Us

Get Job Alerts

Get started
Student Center

Find out more about working at Intel

Learn more
Education

Jobs@Intel Blog

Learn more

Grow your network of opportunities