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Job ID: JR0053939
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Massachusetts, Hudson; US, Oregon, Hillsboro;
Job Type:

Sr. Pre-Si Verification Engineer

Job Description
  • We are seeking an experienced validation engineer to work with a dynamic team designing Intel's next generation IP for High Performance Computing and Artificial Intelligence products. Experience working on pre-Silicon validation required. Familiarity with pre-Silicon simulation tool flows required.

  •  Example tools include but not limited to:

    - Synopsys VCS, Verdi and DVE Knowledge of UVM/OVM including developing verification test benches and constrained random validation highly desirable

    - Experience with modern CPU architecture, such as memory cache hierarchy is desirable

    - Demonstrated ability to create and execute test plans for wide feature set is desired

    - Ability to debug and root cause failure signatures at RTL level is strongly desired

    - Scripting and tool flow automation knowledge, such as Python/Perl, is a plus

    - Knowledge of using emulation platform as a pre-silicon validation vehicle is a plus

    - Candidate should display high degree of independence and proven ability to set and meet own goals

    - Candidate should possess excellent written and oral communication skills



Qualifications

Must have a BS or MS in Electrical Engineering, Computer Engineering, or Computer Science and 5+ years of experience in RTL/Logic design on ASIC’s or IP blocks or SOC's using System Verilog RTL coding.

***Please be informed that Intel is proactively trying to find candidates for  Sr. Pre-Si Verification Engineer and that this position may not be avail

  • UVM/OVM testbench experience
  • Strong background in computer architecture
  • Strong analytical ability, problem solving and communication skills
  • Ability to work independently and at various levels of abstraction
  • Demonstrable experience writing System Verilog
  • Programming experience in C++, Perl and Assembly Algorithms and digital logic
  • Familiarity with a range of internal and 3rd-party logic design tools
  • Strong communication and team work stills.

Inside this Business Group



Other Locations
US, Massachusetts, Hudson; US, Oregon, Hillsboro;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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