Digital hardware is often developed with many parameters to support reuse and late adaptations. Formal verification tools allow to verify circuit behavior for all possible input stimuli, but usually only for one parameter instance. To realize all promises of parameterized RTL, formal verification tools should be enabled to do verifications that are valid for many, ideally all parameter settings.
During the internship a strategy shall be developed to allow such comprehensive formal verifications. The strategy shall be applied to Intel designs.
The internship shall prepare the creation of a master thesis at Intel.
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